1. Field of the Invention
This invention relates to semiconductor fabrication technology, and more particularly, to a method of fabricating a data-storage capacitor for a dynamic random-access memory (DRAM) device.
2. Description of Related Art
As DRAM integration is increased, the various circuit components in a DRAM device are downsized. Fundamentally, a DRAM cell is composed of a field effect transistor (FET) and a data-storage capacitor for storing binary data. The data retaining capability of a DRAM device is proportional to the capacitance of its data-storage capacitor. Therefore when a DRAM device is downsized for higher integration, the capacitance of its data-storage capacitor is also downsized, which would cause the data retaining capability of the downsized capacitor to be reduced. The data retaining capability of the downsized DRAM may thus be unreliable. Moreover, as the capacitance is reduced, the likelihood of soft errors arising from the incidence of (.alpha.-rays increases. To hold data reliably, a DRAM capacitor with a reduced capacitance needs to be more frequently refreshed. One solution to increase the capacitance is to use a dielectric material with a high dielectric constant to form the dielectric layer in the capacitor. The capacitance can also be increased by using a stacked structure to form the capacitor. These solutions, however, are still unable to provide the desired capacitance.
Another solution is to use the so-called trench-shaped capacitor that can help increase the surface area of the electrodes of the capacitor and also help reduce the thickness of the dielectric film so that the capacitance of the capacitor can be increased. This solution, however, results in low yield and low reliability.
Some new high-capacitance capacitor structures, such as the so-called hemispherical-grain polysilicon (HSG polysilicon) capacitor and the reverse-crown capacitor, are now widely used as the data-storage capacitors in DRAMs. The HSG polysilicon capacitor has its bottom electrode formed from HSG polysilicon in such a manner that can help increase the surface area of the bottom electrode and is therefore large in capacitance. Moreover, in a stacked capacitor, the capacitance can be increased by increasing the height of the stacked cells in the capacitor. However, if the height extends to the peripheral circuit area, it causes difficulties in cell planarization and the fabrication of metal interconnects. Therefore, there is a limit to the capacitance that can be increased by using the stacked capacitor. In view of the forgoing problems, there still exists a need in the DRAM industry for new methods that can help further increase the capacitance of the data-storage capacitor in DRAM.